In reply to giridhar.ece@gmail.com:
SystemVerilog has this requirement: tasks can call other tasks and functions, but functions can only call other functions. So when you define a function, you are making a guarantee to the caller of that function that it will not consume time.
The guarantee applies to virtual methods as well. By defining a virtual function in a base class, you are creating a requirement that no override of that method consumes time.
The developers of the UVM (Actually this came from the developers of the AVM, which became the OVM, and then UVM) decided to use functions in the base class for everything but the run phase’s virtual methods to enforce the no time consuming requirement.
Yes, they could have made everything a task and left it to the user to ensure that their tasks did not consume time, but that is an unnecessary freedom that just creates difficult to debug issues later on.