Write a constraint such that data obtained is a increment of previous one

SystemVerilog
1

Here i need to generate a random data where the data should be the incremented value of previous one. Suppose if a first random value generated is 5 then next numbers should be 6,7,8,… Below is the code which i have tried can anyone help me on this

class unique_elements;
rand bit [3:0] data ;
rand bit [3:0] addr;

constraint data_c { foreach (data [i])
if (data[i] && i>0)
data == data +1;}
endclass

module data_increment;

initial begin
unique_elements pkt;
pkt = new();
repeat(10) begin
pkt.randomize();
$display(“data = %p”,pkt.data);
$display(“addr = %d”,pkt.addr);

end
end

endmodule

2

In reply to ranju.ranjitha555@gmail.com:


data == const'(data) +1;

works on questa

3

In reply to ssureshg_:
Your solution always starts a 0.

In reply to ranju.ranjitha555@gmail.com:

You probably should add a constraint that prevents the increment from overflowing based on the number of times you expect to call randomize.

class A;
  rand bit [15:0] data, increment;
  constraint c_incr {
    (const'(increment) != 0) -> {
      increment == const'(increment);
      data == const'(data) + increment;
    }
    increment inside {[1:10]};
  }
endclass

module top;
  A a = new();
  initial repeat(10) begin
    assert(a.randomize());
    $display("%p",a);
  end
endmodule
4

In reply to dave_59:

Thank you, now I understand, you have solved ‘always starts at 0’ issue with


(const'(increment) != 0) -> {...
//in combination with
increment inside {[1:10]};
5

In reply to dave_59:

In reply to ssureshg_:
Your solution always starts a 0.
In reply to ranju.ranjitha555@gmail.com:
You probably should add a constraint that prevents the increment from overflowing based on the number of times you expect to call randomize.

class A;
rand bit [15:0] data, increment;
constraint c_incr {
(const'(increment) != 0) -> {
increment == const'(increment);
data == const'(data) + increment;
}
increment inside {[1:10]};
}
endclass
module top;
A a = new();
initial repeat(10) begin
assert(a.randomize());
$display("%p",a);
end
endmodule

Hi Dave this if this need to be achieved without const keyword how could this be done
Is this const keyword is feasible with other simulators except Mentor questa?
As i tried to execute this with other simulators i’m seeing Error related to const.Can u suggest me how this can be resolved?

6

In reply to ranju.ranjitha555@gmail.com:
https://verificationacademy.com/forums/systemverilog/array-randomization-1

7

In reply to dave_59:

Thanks Dave I got the solution