Write a constraint such that data obtained is a increment of previous one

SystemVerilog
3

In reply to ssureshg_:
Your solution always starts a 0.

In reply to ranju.ranjitha555@gmail.com:

You probably should add a constraint that prevents the increment from overflowing based on the number of times you expect to call randomize.

class A;
  rand bit [15:0] data, increment;
  constraint c_incr {
    (const'(increment) != 0) -> {
      increment == const'(increment);
      data == const'(data) + increment;
    }
    increment inside {[1:10]};
  }
endclass

module top;
  A a = new();
  initial repeat(10) begin
    assert(a.randomize());
    $display("%p",a);
  end
endmodule