Why is my Verilog code for jk flip flop showing dont care in outputs?

SystemVerilog
, ,
1 
module jkff3(
    input j,
    input k,
    input clk,
    inout q3,
    inout q4,
	 output q,
	 output q1
    );
wire k1,j1;
and n1(k1,q3,k,clk);
and n2(j1,q4,j,clk);
nor n3(q3,k1,q4);
nor n4(q4,j1,q3);
assign q=q3;
assign q1=q4;
endmodule

//edit i did a mistake in this code i did not assign q and q1 as q3 and a4 previously

2

In reply to aritrakunda3:
Show your testbench.

3

In reply to dave_59:
//the code

module jkff3_test2;

// Inputs
reg j;
reg k;
reg clk;

// Outputs
wire q;
wire q1;

// Bidirs
wire q3;
wire q4;

// Instantiate the Unit Under Test (UUT)
jkff3 uut (
	.j(j), 
	.k(k), 
	.clk(clk), 
	.q3(q3), 
	.q4(q4), 
	.q(q), 
	.q1(q1)
);

initial begin
	// Initialize Inputs
	j = 0;
	k = 0;
	clk = 0;

	// Wait 100 ns for global reset to finish
	#100;
  j=1;

k=0;
clk=1;
#100;
j=0;
k=0;
clk=1;
#100;
// Add stimulus here

end

endmodule

4

In reply to aritrakunda3:
//the timing diagram
Your text to link here…

5

In reply to aritrakunda3:

Here q3 and q4 are used in ANDing operation but you do not have any driver for q3 and q4. Moreover, I don’t understand why the ports are the ports q3 and q4 required? These should be internal wires.