Why is my Verilog code for jk flip flop showing dont care in outputs?

SystemVerilog
, ,
3

In reply to dave_59:
//the code

module jkff3_test2;

// Inputs
reg j;
reg k;
reg clk;

// Outputs
wire q;
wire q1;

// Bidirs
wire q3;
wire q4;

// Instantiate the Unit Under Test (UUT)
jkff3 uut (
	.j(j), 
	.k(k), 
	.clk(clk), 
	.q3(q3), 
	.q4(q4), 
	.q(q), 
	.q1(q1)
);

initial begin
	// Initialize Inputs
	j = 0;
	k = 0;
	clk = 0;

	// Wait 100 ns for global reset to finish
	#100;
  j=1;

k=0;
clk=1;
#100;
j=0;
k=0;
clk=1;
#100;
// Add stimulus here

end

endmodule