I came across a situation where I would like to compile a module to check syntax. The module used interface for port declaration. However, complier reported error saying that interface couldn’t be implicitly instantiated. After explicitly instantiated the interface, the compilation passed.
After checking IEEE1800, the standard does clearly state that “in contrast to module and program, interfaces are never implicitly instantiated.” I don’t know why interfaces couldn’t be implicitly instantiated in SV/Simulator implementation. What harm does it do if compiler implicitly instantiated it? Trying to understand the underlining mechanism here.
Maybe Dave Rich can share thoughts why this is imposed in IEEE1800? Thx.
IMHO, Verilog/SystemVerilog has way too many implicit defaults. This is a Hardware Description Language after all.
The specific issue here is you are not allowed to leave interface ports of a module unconnected. An interface port is essentially a reference to another instance. The same requirement is placed on ref ports or variables passed by reference to tasks and functions—they must be connected to an actual instance of a variable. To make a connection, you need another module at higher level than the module with the interface port. The top module is the only module that gets implicitly instantiated, so implicitly instantiating an interface at the top level would not really help.