In reply to yeewang822:
You wanted some thoughts…
IMHO, Verilog/SystemVerilog has way too many implicit defaults. This is a Hardware Description Language after all.
The specific issue here is you are not allowed to leave interface ports of a module unconnected. An interface port is essentially a reference to another instance. The same requirement is placed on ref ports or variables passed by reference to tasks and functions—they must be connected to an actual instance of a variable. To make a connection, you need another module at higher level than the module with the interface port. The top module is the only module that gets implicitly instantiated, so implicitly instantiating an interface at the top level would not really help.