Variable accessible inside a class but becomes read-only outside the class?

SystemVerilog
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1

How can I make a read-only variable?
I want this variable to be writeable inside a class but I want it to be read-only when accessed outside the class.
Local and protected type of encapsulation is not readable when accessed outside the class. Instance constant data type can be readable outside the class but changing the value of this variable is only possible during class construction. I don’t want that because all my class variables will reset to its default values when the class is constructed again.

So, is there a way to make a variable that can be accessed inside the class but becomes read-only outside the class?

2

In reply to Reuben:

The way to do this it to write class accessors methods.

See Using Accessors and Mutators in Java

3

In reply to dave_59:

Hi Dave,

Do we have accessors/mutator method implementation in UVM.
If not, would Accellera committee has any plans to implement it?

Thanks,
Siva

4

In reply to Reuben:

Hello, is this what you were asking?


class v;
  protected int name=56;
  function int get_var ();
    return name;
  endfunction
endclass

module p;
  v myc = new();
  initial begin
    $display("Variable with class funct: %0d",myc.get_var());
    // Error-[SV-ICVA] Illegal class variable access
    // $display("Variable with class funct: %0d",myc.name);
  end
endmodule

The way to do this it to write class accessors methods.

Is the above code what you meant about accessors methods in Java?

Regards