Using Macros to create Covergroups

SystemVerilog
, ,
1

Hi all,
I am trying to automate the process of creating covergroups and sampling of bins in it.
Below is a code snippet.

class abc;
define CVG(STR,MAX) \ covergroup ``STR`` ; \ STR``_arg2: coverpoint var_i { bins ``STR``_bin_[] = {[0:``MAX``]}; \ bins error[] = {default}; } \ endgroup CVG(grp1,15)
`CVG(grp2,7) // … ~ 200 more calls

function new;
grp1 = new;
grp2 = new; // … new for all groups
endfunction

task sampler(arg, arg1); //called from somewhere else
case(arg1):
“grp1” : grp1.sample();
“grp2” : grp2.sample(); /// … similar sampling calls for all cases
endcase
endtask
endclass

So, I have this code working as intended. Now I want to automate the function new and *.sample() call by using some macro to decrease the manual effort.
Can someone suggest some way to get this done?
I have tried to include function new in the CVG macro but then it’ll create function new n number of times and throws errors.

Thanks,
Sarvesh

2

In reply to __SarVesH:

It’s possible, but it would be quite convoluted. Your request is similar to what the UVM field macros like `uvm_file_int() do. It involves building a giant task that is used for both constructing and sampling, and you call it with an argument that says which you want to do.

You might be better off using a python/perl scrip o generate the code rather than use macros.