Use of Sequence inside clocking block

SystemVerilog
, ,
1

Hi

recently I have seen sequence is used inside clocking block.

What is the use of that? How to apply it for development?

clocking sck @(posedge pclk);
input paddr, psel, penable, pwrite, pwdata;
output prdata;

sequence at_posedge;
1;
endsequence : at_posedge
endclocking: sck

Thanks
AnantharajTV

2

The only possible advantage of declaring sequences and properties in clocking blocks is the sampling time. Specifically,

If a variable is an input variable of a clocking block, the variable shall be sampled by the clocking block with #1step sampling. Any other type of sampling for the clocking block variable shall result in an error. The sampled value of a such variable is the sampled value produced by the clocking block.

I don’t recommend declaring sequences or properties in clocking blocks; most users don’t, as it complicates things and readability. BTW, you cannot have assertion statements in clocking blocks.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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