Hello,
I have a task that receives a logic as a ref, e.g. :
task MyTask(ref logic ref_input)
I send this task signals from an interface. If the signal is a single bit it works OK, but I cannot use a one bit slice from a packed array as input. i.e. :
interface myInterface
logic myBit;
logic [7:0] myByte;
…
SystemVerilog does not allow a select of a packed array to be passed by reference. Do you really need pass by reference, or will input or output work for you?
Can you pass then entire byte by ref to the task, then select the bit inside the task? You can add an extra argument that indicates which bit to select.
Hi,
No,because what I want is a general task. Sometimes the signal I will send is a single bit, and in other cases it will be a single bit from an array(that can be either packed or unpacked).In such a case, I cannot assume I know the size of the array in advance.
i.e. I might need :
logic myBit;
logic [7:0] myByte;
logic [31:0] myWord;
…
MyTask(myBit,0); //Argument is the signal
MyTask(MyByte,6); //Argument is bit #6 of the signal
MyTask(MyWord,18); //Argument is bit #18 of the signal