Turn Off Assertions When Failed

SystemVerilog
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1

1.) Do you use the following when you want to turn-off assertions when it fails? Why yes or why not? The reason why I asked because I see a post here where the solution is to use $assertoff() in the else statement of the assertion.

$assertfailoff()
$assertcontrol()

2.) What is the syntax or arguments for these system functions?

3.) I think sometimes $assertfailoff() is not recognized by some tools? Is this correct?

2

In reply to Reuben:
See assumptions for specific property | Verification Academy

On item “1”, you are correct. On the why

  1. assertions off during initialization until things settle
  2. Upon a failure in order to ignore further flags and to continue simulation at a faster rate

On “3” The $assertcontrol came in 2017. Talk to your vendor with regards to implementation.
The assert tasks provide backward compatibility to IEEE 1800-2009 and includes the following keywords: $assertoff, $assertkill, and $asserton. Specifically,

  1. $assertoff stops the checking of all specified assertions until a subsequent $asserton. An assertion that is already executing, including execution of the pass or fail statement, is not affected. It is equivalent to:
    $assertcontrol(4, 15, 7, levels [,list])
  2. $assertkill aborts execution of any currently executing specified assertions and then stops the checking of all specified assertions until a subsequent $asserton. It is equivalent to:
    $assertcontrol(5, 15, 7, levels [,list])
  3. $asserton re-enables the execution of all specified assertions. It is equivalent to: $assertcontrol(3, 15, 7, levels [,list])
  4. There is NO $assertfailoff()

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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