SystmeVerilog Assertions -> operator

I understand that [-> m] is a non-consecutive GoTo operator and can be used as (e.g.)

@(posedge clk) a |=> b [->2] ##1 c;

But I came across an example, where I see (in the middle of a property), a → b. What does that mean? Does it mean if a is true that b should be true? Does it behave like an overlapping implication operator? Please see the example below. Thanks.

property count_event(reg [15:0] PerfCtr, reg [15:0] event_count);

@(posedge DfiClk)

disable iff (disable_perfcntcheck)

((PWR_OK === 1’b1) && (Reset === 1’b0) && (DebugPerfCtrEn === 1) && (dfi_event_select === 1) && ($rose(dfi_event))) |->

##[1:5] !$isunknown(capture_dly) && (!capture_dly → event_count == PerfCtr) ##1 !$isunknown(capture_dly) && (capture_dly → event_count == PerfCtr);

In reply to a72:
Per 1800’2017 The logical implication expression1–> expression2 is logically equivalent to (!expression1 || expression2), and the logical equivalence expression1 <–> expression2 is logically equivalent to ((expression1–> expression2) && (expression2–> expression1)). Each of the two operands of the logical equivalence operator shall be evaluated exactly once.

Thus,


a |->  b-> c; // states 
// if(a==0) the property is vacuously TRUE 
// If(a==1) the consequent is evaluated and must be true for a true assertion 
//            Note that there is in assertions vacuity, vacuous true or nonvacuous true
//            A consequent that is a sequence is never vacuous. 
// For the consequent to be true either one of these 2 conditions
//     if(b==0) the expression is TRUE (no vacuity in expressions, only in assertions)
//     if(c==1) the expression is TRUE
//Thus, if you think about it, there is a sort of parallelism in thoughts 
//  in the logical implication and the property implication.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: * Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
  1. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/