SystemVerilog constraints dist behavior

SystemVerilog
, ,
1

Given the below constraint, I was expecting to see addr_1 take up values with this distribution 511:=70, 510:=70, 509:= 70, 508:= 70 …500:= 70 and 31:= 60.
But when I run the below code I see that addr_1 is taking up only value of 31.
Please let me know what I’m missing here.


class packet;
  rand bit [8:0] addr_1;
  
  constraint addr_1_range {   addr_1 dist { [511:500] := 70, 31 := 60 }; }
endclass

module constr_dist;
  initial begin
    packet pkt;
    pkt = new();
    $display("------------------------------------");
    repeat(10) begin
      pkt.randomize();
      $display("\taddr_1 = %0d",pkt.addr_1);
    end
    $display("------------------------------------");
  end
endmodule
2

In reply to dyn_verif:
I am puzzled by your results. The only thing wrong I see is the range, instead of { [511:500]
it should be upward { [500:511].
I also believe that the randomizer computes the space of values, it computes


dist { [500:511] := 1, 31 := 1};
as
500, 501, 502, .. 511, 31
Meaning that the 31 has a probability of 1/13

Below worked for me.


class packet;
    rand bit [8:0] addr_1;   
    constraint addr_1_range {   addr_1 dist { [500:511] := 1, 31 := 10}; }
  endclass

module top;
    `include "uvm_macros.svh"   import uvm_pkg::*;
    bit clk, a, b, reset_n;
    bit[8:0] v; 
    packet pkt;
    initial forever #10 clk = !clk; 
  
    initial begin         
      pkt = new();
      repeat (200) begin
        @(posedge clk);
        if (!randomize(pkt, v, b) with {
          v   dist {[500:511] := 1 , 30 := 1};
          b   dist {1'b1 := 1, 1'b0 := 2}; 
        }) `uvm_error("MYERR", "This is a randomize error"); 
        $display("\taddr_1 = %0d, v=%d",pkt.addr_1, v);
      end
      $finish;
    end
  endmodule
  	addr_1 = 31, v=507
# 	addr_1 = 503, v=511
# 	addr_1 = 500, v=509
# 	addr_1 = 511, v=500
# 	addr_1 = 31, v=506
# 	addr_1 = 505, v=502
# 	addr_1 = 505, v=500
# 	addr_1 = 510, v=502
# 	addr_1 = 503, v= 30
# 	addr_1 = 31, v=501
# 	addr_1 = 502, v=503
# 	addr_1 = 501, v= 30
# 	addr_1 = 508, v=510
# 	addr_1 = 502, v=510
# 	addr_1 = 505, v=509
# 	addr_1 = 31, v=507
# 	addr_1 = 31, v= 30
# 	addr_1 = 504, v=500
# 	addr_1 = 506, v=500
# 	addr_1 = 501, v=503
# 	addr_1 = 31, v=505
# 	addr_1 = 508, v=505
# 	addr_1 = 31, v=508
# 	addr_1 = 508, v=503
# 	addr_1 = 501, v=503
# 	addr_1 = 31, v=502
# 	addr_1 = 506, v=502
# 	addr_1 = 31, v=506
# 	addr_1 = 505, v=505
# 	addr_1 = 31, v=510
# 	addr_1 = 31, v=510
# 	addr_1 = 31, v=504
# 	addr_1 = 504, v=502
# 	addr_1 = 511, v=504
# 	addr_1 = 502, v=501
# 	addr_1 = 505, v=504
# 	addr_1 = 31, v=510
# 	addr_1 = 500, v=509
# 	addr_1 = 31, v=505
# 	addr_1 = 31, v=509
# 	addr_1 = 31, v=501
# 	addr_1 = 31, v=505
# 	addr_1 = 503, v=500
# 	addr_1 = 31, v=500
# 	addr_1 = 505, v=502
# 	addr_1 = 508, v=510
# 	addr_1 = 31, v=509
# 	addr_1 = 31, v=503
# 	addr_1 = 31, v=511

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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3

In reply to ben@SystemVerilog.us:

Thanks Ben
The range was the issue
500:511 worked
511:500 did not work.