System Verilog- How to parse string to instantiate class

Hi,

I am getting a class type and assigning it to a string-

string class_name = r_pkt.get_type_name(); // r_pkt is a class. Name of the class is router_packet.

At this point, string class_name has “router_packet”

Now I want to use this string to parse the class name and instantiate it.

class_name class_h;

basically I want this using class name that I have in string -
router_packet class_h;

How do I achieve it? Is there a system verilog construct that can parse the string and use it as class instantiation?
Please let me know.

In reply to shivamdec:

Generally, there is nothing in SystemVerilog that allows you to convert a string to an identifier. As a compiled language, you cannot form identifiers dynamically at run-time.

However there are schemes to associate strings names with the creation of class objects. The UVM has a mechanism called the “factory” which requires a registration step in the class definition, and then construction with a create_object_by_name() method.

The UVM has an even more efficient factory scheme that avoids the use of string by using a proxy class uvm_object_wrapper and get_type().