System verilog assertion at end of the test

[sharatk]

I want to write an SVA which is triggered at the end of the test.

pseudo code.

cover property end_of_test
@(end_of_test_event)
…
endproperty

Now to procure that even I tried using final block

final
->end_of_test_event;

This does not trigger evaluation of assertion. I guess it has to do something with SV timing regions. Would like to understand more.

What are my alternatives to generate such an event?

[ben2]

In reply to sharatk:

Per 1800’2017: 9.2.3 Final procedures, Concurrent assertions are illegal inside final procedures because the only statements allowed inside a final procedure are those permitted inside a function declaration. Thus, only immediate assertions are allowed inside a final procedure. Concurrent assertions are also illegal in tasks and class methods.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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[dave_59]

In reply to sharatk:

You usually do not need a property for covering the end of the test. The coverage database should keep track of the tests the reach the end without error as an implicit test record. Check your tools documentation.

[sharatk]

In reply to dave_59:

Hey Dave,

Sorry for not being clear. I am not trying to cover the test ended. I want to cover a variable never asserting, throughout the simulation.
I am using final block to assert an event, so that I can trigger the cover assertion statement.

Now, I think we can do it using some UVM signaling. Like when it is at the end of run_phase or better in check_phase, we can use some virtual interface signal for sampling at assertion module.
But I am sure there would be something inbuilt in system verilog since this is hardly a novel challenge.