System verilog assertion at end of the test

Question

I want to write an SVA which is triggered at the end of the test.

pseudo code.

cover property end_of_test
@(end_of_test_event)
....
endproperty

Now to procure that even I tried using final block

final
->end_of_test_event;

This does not trigger evaluation of assertion. I guess it has to do something with SV timing regions. Would like to understand more.

What are my alternatives to generate such an event?

Answer 1

ben@SystemVerilog.us

Full Access

2263 posts

April 21, 2020 at 11:54 pm

In reply to sharatk:

Per 1800'2017: 9.2.3 Final procedures, Concurrent assertions are illegal inside final procedures because the only statements allowed inside a final procedure are those permitted inside a function declaration. Thus, only immediate assertions are allowed inside a final procedure. Concurrent assertions are also illegal in tasks and class methods.

Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home
* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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1) SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
2) https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
3) SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

Answer 2

dave_59

Forum Moderator

9459 posts

April 22, 2020 at 12:33 am

In reply to sharatk:

You usually do not need a property for covering the end of the test. The coverage database should keep track of the tests the reach the end without error as an implicit test record. Check your tools documentation.

— Dave Rich, Verification Architect, Siemens EDA

Answer 3

sharatk

Full Access

38 posts

April 22, 2020 at 10:21 am

In reply to dave_59:

Hey Dave,

Sorry for not being clear. I am not trying to cover the test ended. I want to cover a variable never asserting, throughout the simulation.
I am using final block to assert an event, so that I can trigger the cover assertion statement.

Now, I think we can do it using some UVM signaling. Like when it is at the end of run_phase or better in check_phase, we can use some virtual interface signal for sampling at assertion module.
But I am sure there would be something inbuilt in system verilog since this is hardly a novel challenge.

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