SystemVerilog reference error

SystemVerilog
,
1

Sir ,i am faced the runtime error in “Unresolved reference to ‘h’”.

My program is the master slave communication using the interface from the basic model.

My code is below here:

interface inter(input bit clock,bit ready);
  int address,r_w,rdata,valid, wdata;
 
endinterface



class master1;
     virtual inter intf;
     
      task write1(input [31:0]address1, input [31:0]data1);
  begin
      
      @(posedge intf.clock);
      intf.address=address1;
      intf.wdata=data1;
      intf.valid =1;
      intf.r_w=1;
      $write("write add=%d data=%d \n",intf.address,intf.wdata,$time);
      while (intf.ready!=1)
      begin
        @(posedge intf.clock);
      end
         end
      endtask
   
    
    task read1( input [31:0]address2 );
     
    begin
    $display("i am read 1\n",$time);
     @(posedge intf.clock);
     intf.address=address2;
     intf.valid=1;
     intf.r_w=0;
         $display("\nre add=%0d data=%0d\n",intf.address,intf.wdata,$time);
     while(intf.ready!=1)
     begin
       @(posedge intf.clock);
   
end 
   
   end
     endtask    
    
endclass


class slave1;
     virtual inter intf;
     reg [31:0]mem[1024:0];
 
 

 task slave_op;
 while(1)
 
 begin
   @(posedge intf.clock)
   if(intf.r_w==1 && intf.valid==1)
    begin
      mem[intf.address]=intf.wdata;
      $display("write completed",$time);
     end
   else if(intf.r_w==0 && intf.valid==1)
     begin
       intf.rdata=mem[intf.address];
       $display("read completed=%d",intf.rdata);
     end
 end
 endtask
endclass



module top1;
    inter intf();
    bit clock,ready;
    
    
  initial begin
         master1 h=new();
         slave1 h1=new();
         h.intf=intf;
         h1.intf=intf;
 end
 
 initial
 begin
   fork
    begin 
    #10 h.write1(32'd10,32'd1);
      end
    begin
   #20 h.read1(32'd10) ;
      end
    begin
     #30 h.write1(32'd20,32'd2);
     end
    begin
     #40 h.read1(32'd20) ;
     end
     begin
      #50 h1.slave_op();
     end
  join
   $display("COMPLETE");
  end
  

  
  initial  begin
  
    ready=1;
 
   intf.clock=0;
 forever begin
    #5 intf.clock=~intf.clock;
end

 end 

endmodule
2

In reply to Rajaraman R:

I think you meant mas and sla instead of h. Also you need to declare mas and sla as static variables outside the initial block so that both initial blocks can access them.

3

In reply to Rajaraman R:

There is no reference to h or h1 variable in the code. Use the correct object instance name or handle to access the task inside the class, just as you did for interface assignment.

mas.write1(…) / mas.read1(…)
sla.slave_op()

4

In reply to prabhakaran.gunasekaran:

Thankyou for replaying my queston sir…
i have to change for my code to your suggestion. But the same problem also faced sir. The problem is display the runtime error at “Unresolved reference to ‘h’. and h1”;

5

In reply to dave_59:

Thankyou for replaying me sir…
But i am does’t understand your suggestion.so give me a sample code sir…

6

In reply to Rajaraman R:

The below code is compiling and running…


interface inter(input bit clock,bit ready);
  int address,r_w,rdata,valid, wdata;
endinterface
 
class master1;
  virtual inter intf;

  task write1(input [31:0]address1, input [31:0]data1);
    begin
      @(posedge intf.clock);
      intf.address=address1;
      intf.wdata=data1;
      intf.valid =1;
      intf.r_w=1;
      $write("write add=%d data=%d \n",intf.address,intf.wdata,$time);
      while (intf.ready!=1) begin
        @(posedge intf.clock);
      end
    end
  endtask
 
  task read1( input [31:0]address2 );
    begin
    $display("i am read 1\n",$time);
    @(posedge intf.clock);
     intf.address=address2;
     intf.valid=1;
     intf.r_w=0;
         $display("\nre add=%0d data=%0d\n",intf.address,intf.wdata,$time);
     while(intf.ready!=1) begin
       @(posedge intf.clock);
     end 
 
   end
  endtask    
endclass
 
class slave1;
  virtual inter intf;
  reg [31:0]mem[1024:0];
 
 task slave_op;
   while(1) begin
     @(posedge intf.clock)
     if(intf.r_w==1 && intf.valid==1) begin
        mem[intf.address]=intf.wdata;
        $display("write completed",$time);
     end else if(intf.r_w==0 && intf.valid==1) begin
         intf.rdata=mem[intf.address];
         $display("read completed=%d",intf.rdata);
     end
   end
 endtask
endclass
 
module top1;
  bit clock,ready;
  inter intf(clock,ready);
  master1 h;
  slave1 h1;
 
  initial begin
    h=new();
    h1=new();
    h.intf=intf;
    h1.intf=intf;
  end
 
  initial begin
    fork
     begin 
       #10 h.write1(32'd10,32'd1);
     end
     begin
       #20 h.read1(32'd10) ;
     end
     begin
       #30 h.write1(32'd20,32'd2);
     end
     begin
       #40 h.read1(32'd20) ;
     end
     begin
       #50 h1.slave_op();
     end
    join
    $display("COMPLETE");
  end
 
  initial begin
    ready=1;
    clock=0;
    forever begin
      #5 clock = ~clock;
    end
   end 
endmodule
7

In reply to prabhakaran.gunasekaran:

Thankyou for given code sir…