In reply to Rajaraman R:
The below code is compiling and running…
interface inter(input bit clock,bit ready);
int address,r_w,rdata,valid, wdata;
endinterface
class master1;
virtual inter intf;
task write1(input [31:0]address1, input [31:0]data1);
begin
@(posedge intf.clock);
intf.address=address1;
intf.wdata=data1;
intf.valid =1;
intf.r_w=1;
$write("write add=%d data=%d \n",intf.address,intf.wdata,$time);
while (intf.ready!=1) begin
@(posedge intf.clock);
end
end
endtask
task read1( input [31:0]address2 );
begin
$display("i am read 1\n",$time);
@(posedge intf.clock);
intf.address=address2;
intf.valid=1;
intf.r_w=0;
$display("\nre add=%0d data=%0d\n",intf.address,intf.wdata,$time);
while(intf.ready!=1) begin
@(posedge intf.clock);
end
end
endtask
endclass
class slave1;
virtual inter intf;
reg [31:0]mem[1024:0];
task slave_op;
while(1) begin
@(posedge intf.clock)
if(intf.r_w==1 && intf.valid==1) begin
mem[intf.address]=intf.wdata;
$display("write completed",$time);
end else if(intf.r_w==0 && intf.valid==1) begin
intf.rdata=mem[intf.address];
$display("read completed=%d",intf.rdata);
end
end
endtask
endclass
module top1;
bit clock,ready;
inter intf(clock,ready);
master1 h;
slave1 h1;
initial begin
h=new();
h1=new();
h.intf=intf;
h1.intf=intf;
end
initial begin
fork
begin
#10 h.write1(32'd10,32'd1);
end
begin
#20 h.read1(32'd10) ;
end
begin
#30 h.write1(32'd20,32'd2);
end
begin
#40 h.read1(32'd20) ;
end
begin
#50 h1.slave_op();
end
join
$display("COMPLETE");
end
initial begin
ready=1;
clock=0;
forever begin
#5 clock = ~clock;
end
end
endmodule