In reply to Balerion:
Looking at your definition of the assertion // if data changes time x before clk_gated Final Error should rise after clk_gated rose I see the following method of construction for the assertion. SVA is not going to work here because of the samplings and clocks.
realtime t1, diff=2ns;
always @(data) begin
t1=$realtime;
@(posedge clk_gated) if (($realtime-t1) > diff)
#1 am_ferror: assert(final_err); // The #1 is to account for a delay till final_err rises
end
Basically, you'need to build your own model.
Instead of the
always I started with a
task that is fork-join_none with a trigger, as I explain in my paper
Understanding the SVA Engine (see link below).
However, I could not think of an appropriate trigger since the
@(data) would work.
Anyway, this may provide you with some possible approaches, particularly since you understand the problem better than me.
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
3) Papers:
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
