Signal direction in function

SystemVerilog
,
1

Does the signal direction (input, output, inout) matter in case of argument to a function.
You can see an example below.

// Code your testbench here
// or browse Examples
module x;
  
  function func1 (ref int a);
    a = 10;
    return;
  endfunction
  
  function func2 (int a);
    a = 10;
    return;
  endfunction

  initial begin
    int a;
    func1(a);
    $display ("a = %d", a);
    
    func2(a);
    $display ("a = %d", a);
  end
endmodule

In both the functions, I am actually returning value back to the caller.
In both the functions, I have not declared the argument as an output.
Yet, I am able to pass the value back to caller.

Is the way the tool is working correct?

2

In reply to verif_learner:

Your tool is working fine. ‘a’ was already 10 before calling func2.

3

In reply to dave_59:

In reply to verif_learner:
Your tool is working fine. ‘a’ was already 10 before calling func2.

Dave,

Actually, my question is a little different.
As the caller of the function is getting value of ‘a’, I want to know if we have to specify it as output. If you notice, func1, I have not declared arg as a output.

You can also see the modified code. In func1, I argument is not declared as output while it is in the second case. Func3 results in syntax error indicating that output and ref cannot be declared together.

module x;
  
  function func1 (ref int a);
    a = 10;
    return;
  endfunction
  
  function func2 (output int a);
    a = 10;
    return;
  endfunction

  function func3 (ref output int a);
    a = 10;
    return;
  endfunction

  initial begin
    int a, b, c;
    func1(a);
    $display ("a = %d", a);
    
    func2(b);
    $display ("b = %d", b);
    
    func3(c);
    $display ("c = %d", c);
  end
endmodule
4

In reply to verif_learner:
An argument can have only one direction: input, output, inout, or ref. If you don’t specify a direction for the first argument, it is implicitly ‘input’. The implicit directions for the arguments that follow use the previous arguments direction.

inputs are copied by value upon entry to the task/function. outputs are copied on return. inout are copied on entry and return. ref arguments are never copied. They are direct references to the actual argument variable.

5

In reply to dave_59:

In reply to verif_learner:
An argument can have only one direction: input, output, inout, or ref. If you don’t specify a direction for the first argument, it is implicitly ‘input’. The implicit directions for the arguments that follow use the previous arguments direction.
inputs are copied by value upon entry to the task/function. outputs are copied on return. inout are copied on entry and return. ref arguments are never copied. They are direct references to the actual argument variable.

Ok. I assumed ref and direction to be independent directives.
For example, using ref will make sure that values are not copied.
So, I can use the original value in my function.
Only if I declare it as output, I can also make changes to the signal and return the value.
My interpretation is incorrect obviously.