Signal direction in function

SystemVerilog
,
3

In reply to dave_59:

In reply to verif_learner:
Your tool is working fine. ‘a’ was already 10 before calling func2.

Dave,

Actually, my question is a little different.
As the caller of the function is getting value of ‘a’, I want to know if we have to specify it as output. If you notice, func1, I have not declared arg as a output.

You can also see the modified code. In func1, I argument is not declared as output while it is in the second case. Func3 results in syntax error indicating that output and ref cannot be declared together.

module x;
  
  function func1 (ref int a);
    a = 10;
    return;
  endfunction
  
  function func2 (output int a);
    a = 10;
    return;
  endfunction

  function func3 (ref output int a);
    a = 10;
    return;
  endfunction

  initial begin
    int a, b, c;
    func1(a);
    $display ("a = %d", a);
    
    func2(b);
    $display ("b = %d", b);
    
    func3(c);
    $display ("c = %d", c);
  end
endmodule