Random constraints

SystemVerilog
, ,
1

I found this implementation on a website and I’m trying to understand why they have made a comment saying that the constraint my_error is not a right way of implementation. I can understand that min and max don’t have a value associated with it compare with 0 and 128. But it produces result without any compilation error. Can someone explain?


class MyClass;
		rand bit [7:0] min, typ, max;
		
		// Valid expression
		constraint my_range { 0 < min;
		                      typ < max; typ > min; 
		                      max < 128; }
		                      
		// Use of multiple operators in a single expression is not allowed
		constraint my_error { 0 < min < typ < max < 128; } // This will set min to 16 and randomize all others constraint my_min { min == 16; } // This will set max to a random value greater than or equal to 64 constraint my_max { max >= 64; }
	endclass
2

In reply to nimitz_class:

The comment and explanation are not correct. It’s perfectly legal to write that code; it’s just that it does not produce results you think you should be getting.

This is a common beginner’s mistake. See Asking better questions on the Verification Academy Forums with EDAPlayground - Verification Horizons