Package for parametric design

SystemVerilog
1

Hi,

I need to design & verify parametric design, such that my design & verif env will be instantiated twice, each time with different parameters.
I usually work with packages for my design (system verilog), so all of parameters, structs etc are defined there.
My question:
Is there a way to write such package so same package will hold same parameter with two different values? (different value for each instance)
Is there a robust way in uvm to verify such design?
Thanks!

2

In reply to idol:

SystemVerilog does not provide a mechanism to choose between different definitions of the same package. Some tools may let you create separate design units bound with different, but you will need to make sure that works across your entire tool chain.

A better option would be to create separately named packages and use each to override the parameters when instantiating your DUT.

package A;
parameter P = 1;
endpackage
package B;
parameter P = 2;
endpackage
module DUT #(int P) (ports);
...
endmodule

module test;

  DUT #(.P(A::P)) DUT1 (ports);
  DUT #(.P(B::P)) DUT2 (ports);
endmodule
3

In reply to dave_59:

Another solution is to declare parameterized classes within the packages.
Then override the parameter both to the DUT and the class.

package A;
  class foo_c #( parameter P = 1 );
// foo_c body
  endclass
endpackage

module test;
  localparam P1 = 1;
  localparam P2 = 2;
  DUT      #( .P( P1 ) ) DUT1 ();
  A::foo_c #( .P( P1 ) ) P1_test = new();

  DUT      #( .P( P2 ) ) DUT2 ();
  A::foo_c #( .P( P2 ) ) P2_test = new();
endmodule

Regards,

Mark

4

In reply to Mark Curry:

Hi,
I need also my design to support two different values for same parameter under same package.
So two different instantiations will actualy hold two values for the exact same parameter in package.
(example:
package A;
localparam Tx = 5
endpackage

For one instance use value of Tx=5. for second instance, use value of Tx=4
)

5

In reply to idol:

In reply to Mark Curry:
Hi,
I need also my design to support two different values for same parameter under same package.
So two different instantiations will actualy hold two values for the exact same parameter in package.
(example:
package A;
localparam Tx = 5
endpackage
For one instance use value of Tx=5. for second instance, use value of Tx=4
)

As I said above, SystemVerilog does not allow this.