Package for parametric design

SystemVerilog
2

In reply to idol:

SystemVerilog does not provide a mechanism to choose between different definitions of the same package. Some tools may let you create separate design units bound with different, but you will need to make sure that works across your entire tool chain.

A better option would be to create separately named packages and use each to override the parameters when instantiating your DUT.

package A;
parameter P = 1;
endpackage
package B;
parameter P = 2;
endpackage
module DUT #(int P) (ports);
...
endmodule

module test;

  DUT #(.P(A::P)) DUT1 (ports);
  DUT #(.P(B::P)) DUT2 (ports);
endmodule