Package for parametric design

SystemVerilog
3

In reply to dave_59:

Another solution is to declare parameterized classes within the packages.
Then override the parameter both to the DUT and the class.

package A;
  class foo_c #( parameter P = 1 );
// foo_c body
  endclass
endpackage

module test;
  localparam P1 = 1;
  localparam P2 = 2;
  DUT      #( .P( P1 ) ) DUT1 ();
  A::foo_c #( .P( P1 ) ) P1_test = new();

  DUT      #( .P( P2 ) ) DUT2 ();
  A::foo_c #( .P( P2 ) ) P2_test = new();
endmodule

Regards,

Mark