Looking for an exercise materials to challenge myself in SystemVerilog and UVM preferably with solution

SystemVerilog
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Hi All,

I’m good at basic SystemVerilog and UVM but now i would like to use those skills in some practical problems which will challenge me in getting the solution, could you please suggest some good links/online materials that i can use it. It will be better if i get solutions too with it but its not mandatory.

Thanks for your support!

Cheers!

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In reply to vvv:

Start from development of basic testbench environment for protocols like APB, SPI, AHB etc. You can find specifications from ARM, ST, TI etc.

Go through Coverage Cookbook HERE and UVM Cookbook HERE to know about verification Plan and Testbench Architectures.

Also see reference implementations of protocols like APB and AHB HERE.

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In reply to mayurkubavat:

Thank you mayurkubavat,
Its a great link to follow.

In addition, I’m also looking for quick problems similar to the ones asked in interviews.
For eg, Round robin arbitration (for which i know the solution)or any other questions to exercise my skills.

Do you think you a]know any ??

Thanks in advance!