Issue with using $countones in constraint

SystemVerilog
, ,
1

Hi all,

I’ve wrote the following code:


    rand bit [7:0]  p_disable;
    rand bit [19:0] v_disable ;
    
    constraint dis_1_c { 
        (sp.p_rand_en == 0) -> (p_disable == 0);
        (sp.v_rand_en == 0) -> (v_disable == 0);
    };
    
    constraint dis_4_c {
        sp.v_rand_en -> (($countones(~(v_disable[19:0])) >= $countones(~(p_disable[7:0]))));
    };
    constraint dis_6_c {    
        solve p_disable before v_disable hard;
    };

sp.p_rand_en & sp.v_rand_en are bits and are set before randomization.

I’m using VCS and I get the following error regardless of these enables values:

=======================================================

Solver failed when solving following set of constraints

bit[0:0] stress_picker.astro_virtual_way_rand_en = 1’h0;
bit[19:0] fv_temp_122 = 20’h97e8b;
rand bit[19:0] v_disable; // rand_mode = ON

constraint dis_1_c // (from this) (constraint_mode = ON) (/p/mpg/roeynaga_wa/ASTRO_ICL_A0/astro-icl-j0-18ww04a_atag/verif/tb/common/astro_global_config.sv:199)
{
(stress_picker.astro_virtual_way_rand_en == 1’h0) → (v_disable == 20’h0);
}
constraint dis_4_c // (from this) (constraint_mode = ON) (/p/mpg/roeynaga_wa/ASTRO_ICL_A0/astro-icl-j0-18ww04a_atag/verif/tb/common/astro_global_config.sv:204)
{
(fv_temp_122 == (~v_disable));
}

=======================================================

Do you have any idea what is wrong with my code?

2

In reply to i_roey:

The constraint solver is solving without any issues,when the ‘hard’ keyword is removed. See this link.
What is the reason to specify the ‘hard’ explicitly? By default constraints are hard.

3

In reply to S.P.Rajkumar.V:

Hi S.P.Rajkumar.V,

Thanks for your replay and when running without “hard” the solver doesn’t fail.

But, I don’t fully agree with this solution and here is why:

  1. If “solve … before …” is hard by default, than removing it changes nothing and the solver should still fail.
  2. Even when “sp.v_rand_en” equal zero the solver still fails. But, In that case, “dis_4_c” shouldn’t bother the solver at all.
4

In reply to i_roey:

Yes, I didn’t fully understand the root of the issue. So, I just posted the solution in the hope that it helps to continue with your work. Also, when you remove ‘hard’ again VCS solves without any issues, even in the case of v_rand_en equal to zero.

Here are some more observations I didn’t post earlier:

  1. I couldn’t find any keyword such as ‘hard’ in SV-2012 LRM. All the examples in LRM has only ‘soft’ to differentiate soft constraints.
  2. When I choose IRUN in the eda playground example link I shared, it throws some compile error for ‘hard’ keyword too.
  3. Where-as VCS gives constraint failure. So, it makes me think that VCS is doing something extra on top of SV LRM.

So, better to talk to your EDA Vendor, or wait for the experts in this forum to comment.

5

In reply to S.P.Rajkumar.V:

S.P.Rajkumar.V, Thanks!

Let’s wait for the experts in this forum.