Issue with using $countones in constraint

SystemVerilog
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3

In reply to S.P.Rajkumar.V:

Hi S.P.Rajkumar.V,

Thanks for your replay and when running without “hard” the solver doesn’t fail.

But, I don’t fully agree with this solution and here is why:

  1. If “solve … before …” is hard by default, than removing it changes nothing and the solver should still fail.
  2. Even when “sp.v_rand_en” equal zero the solver still fails. But, In that case, “dis_4_c” shouldn’t bother the solver at all.