Issue with using $countones in constraint

SystemVerilog
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4

In reply to i_roey:

Yes, I didn’t fully understand the root of the issue. So, I just posted the solution in the hope that it helps to continue with your work. Also, when you remove ‘hard’ again VCS solves without any issues, even in the case of v_rand_en equal to zero.

Here are some more observations I didn’t post earlier:

  1. I couldn’t find any keyword such as ‘hard’ in SV-2012 LRM. All the examples in LRM has only ‘soft’ to differentiate soft constraints.
  2. When I choose IRUN in the eda playground example link I shared, it throws some compile error for ‘hard’ keyword too.
  3. Where-as VCS gives constraint failure. So, it makes me think that VCS is doing something extra on top of SV LRM.

So, better to talk to your EDA Vendor, or wait for the experts in this forum to comment.