Hi all ,
I am trying to figure out if there’s any difference with int’() Cast VS 32’() Cast !!
(1) I have following Code with int’() Cast ::
rand bit [1:0] b [10] ;
constraint INT_SUM { b.sum() with ( int'( item ) ) == 20 ; }
Now I understand that int’( item ) would Help achieve the result of sum() using 32-bits .
[Q1] But since int is Signed type would it be a Signed addition too ?
The RHS ( 100 ) is by default Signed and an expression is a Signed Expression if all the Operands are Signed .
bit is by default unsigned but would the int’() Cast be interpreted as (1) OR (2) ?? ::
(1) 32'( signed'( b[0] ) ) + 32'( signed'( b[1] ) ) + .... 32'( signed'( b[9] ) ) == 32'ds20 ;
(2) signed'( 32'( b[0] ) ) + signed'( 32'( b[1] ) ) + .... signed'( 32'( b[9] ) ) == 32'ds20 ;
[Q2] Would it Interpreted as (1) OR (2) ??
[2] Similarly if I use the Size Cast for Unpacked Array of Signed Elements ::
rand bit signed [1:0] b [10] ;
constraint SUM_32 { b.sum() with ( 32'( item ) ) == 20 ; } // RHS is Signed by default !!
(i) Any expression with Unsigned Operand is treated as Unsigned expression
(ii) A sized literal is Unsigned
So clubbing (i) and (ii)
[Q3] Would the expression be evaluated as Unsigned due to 32’() i.e
( EDIT :: ) Having a sized literal of 32’( item ) ??
In reply to TC_2017:
[A1] Yes, it is performing signed addition. That not a problem until the sum has a potential to be larger than 31 bits.
[A2] int’(expr) is the same as (2). The difference is in the sign extension.
[A3] Not sure what you mean. Everything is signed; there are no sized literals.
In reply to dave_59:
For [3] ::
EDIT :: Eg =>
100 is by default 32-bit Signed . However Sized Literal 32’d100 is 32-bit Unsigned .
So using the Same Verilog basic rules with constraint SUM_32
Would the size cast of 32’( item ) cause the Expression be treated
as Unsigned ?
In reply to TC_2017:
Don’t see any 100 or 32’d100 in any code you have posted.
In reply to dave_59:
My apologies I meant them as an example .
Have edited the above reply
In reply to TC_2017:
I’m still not following you. Please enter a complete example.
In reply to dave_59:
Hi Dave ,
With Constraint SUM_32 the expression is Unrolled to ::
32'( b[0] ) + 32'( b[1] ) + ... + 32'( b[9] ) == 20 ; // Unrolled Expression
Now based on basic Verilog Arithmetic rules ::
(i) An unsized Integer is Considered Signed . Hence 20 would be 32-bit Signed above
(ii) A sized Integer ( Eg: 32'd20 ) is Considered Unsigned .
So based on (i) RHS of Constraint Expression ( i.e 20 ) is 32’ds20 ( 32-bit Signed )
Based on (ii) would LHS :: 32’( b[0] ) + 32’( b[1] ) + … + 32’( b[9] )
be treated as Signed or Unsigned ? i.e
[Q] Would it perform 0-Paddding OR Sign Extension for the elements ?
0-Padding due to the Size Cast ( 32’( b[0/1/…/9] ) ) since Sized Literal is Unsigned
( hence 0-Padding )
**0-Padding would make the Constraint Expression Unsigned
Sign Extension would make the Constraint Expression Signed**
In reply to TC_2017:
The reduction methods are always evaluated in the context of each element type, or the type of the ‘with’ clause. Even though when in a constraint we say that the reduction operator gets unrolled, it still has to evaluate the same way as if it was not in a constraint. So none of the context outside the sum() method effects the expression inside.
In reply to dave_59:
“So none of the context outside the sum() method effects the expression inside”
By this I understand that RHS of the expression doesn’t play a part in how
the expression is Evaluated.
My confusion is since the elements of Unpacked Array are Signed ,
would the 32’() Size Cast within the with() clause ( 32’(item) ) ,
result in 0-Padding Or Sign Extension ( based on MSb of its respective elements )
for each element ??
[2] Consider the following ( Somewhat related to above Constraints ) Simple Expressions ::
(i) rand bitsign a , b ; // typedef bit signed [ 3:0] bitsign ;
a + b == 10 ; // Unsized Integer treated as 32'ds10 !!
(ii) rand bitsign a , b ; // typedef bit signed [ 3:0] bitsign ;
a + b == 32'd10 ; // Sized Integer treated as Unsigned i.e 32'd10 !!
For (i) and (ii) above is there a difference in Size Extension for LHS ?
Would (i) have Sign Extension ( Since RHS is Signed ) and
(ii) have 0-Padding ( Since RHS is Unsigned ) ?