In reply to dave_59:
Hi Dave ,
With Constraint SUM_32 the expression is Unrolled to ::
32'( b[0] ) + 32'( b[1] ) + ... + 32'( b[9] ) == 20 ; // Unrolled Expression
Now based on basic Verilog Arithmetic rules ::
(i) An unsized Integer is Considered Signed . Hence 20 would be 32-bit Signed above
(ii) A sized Integer ( Eg: 32'd20 ) is Considered Unsigned .
So based on (i) RHS of Constraint Expression ( i.e 20 ) is 32’ds20 ( 32-bit Signed )
Based on (ii) would LHS :: 32’( b[0] ) + 32’( b[1] ) + … + 32’( b[9] )
be treated as Signed or Unsigned ? i.e
[Q] Would it perform 0-Paddding OR Sign Extension for the elements ?
0-Padding due to the Size Cast ( 32’( b[0/1/…/9] ) ) since Sized Literal is Unsigned
( hence 0-Padding )
**0-Padding would make the Constraint Expression Unsigned
Sign Extension would make the Constraint Expression Signed**