How to wait on a clocking block signal with timeout functionality

SystemVerilog
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1

When I have to wait for signal, I usually use statement like @(cb iff signal == condition)

However, the issue in such statement is that the if the clocking block keeps waiting then it is harder to trace back. Therefore, I end up using while loop with clock cycles threshold for the ease for debug but this increases verbosity. Such as
while(!condition) begin
@(cb);
if(cycle count)
FATAL;
end

Therefore, is there anyway where I can add timeout condition in clocking block , for example, @(cb iff signal with timeout)?

2

check this, I have use simple clk, but you can use clocking block as well.
Thanks,
Juhi Patel.
https://www.linkedin.com/in/juhi-patel-455535149/

3

In reply to Juhi_Patel:

Not exactly sure what you need to do, but you could try

fork
  @(cb iff signal == condition);
  wait(cycle_cout == something);
join_any
disable fork; // gets rid of other hanging threads
if (cycle_cout == something)
   // then you timed out;
else
   // otherwise you didn't
4

In reply to Juhi_Patel:

Hey Juhi,
rather than assigning value to B, you can also wait for A==15 in fork and that would work fine right. just trying to use less variables and always code block.
thanks

5

In reply to Blitzz0418:
Yes sure, you’re correct. But i just wanted to give one example and i had idea that b always goes high when a value is reaching to 15 and busy waiting is done on b.

Thanks,
Juhi Patel.
https://www.linkedin.com/in/juhi-patel-455535149/

6

In reply to dave_59:

In reply to Juhi_Patel:
Not exactly sure what you need to do, but you could try

fork
@(cb iff signal == condition);
wait(cycle_cout == something);
join_any
disable fork; // gets rid of other hanging threads
if (cycle_cout == something)
// then you timed out;
else
// otherwise you didn't

This is how I have been using in my simulations and it works well. Thank you.