How to drive the signals which is inside DUT

SystemVerilog
1

I pasted some code here and what I want to do is to drive the bundle of valid signals (valid1, valid2, valid3, valid4) in the B_inst inside DUT.


module A (input clk, 
          input rst,
          ...,
          output v1,
          output v2,
          output v3,
          output v4);
endmodule

module B (input clk, 
          input rst,
          ...,
          input valid1,
          input valid2,
          input valid3,
          input valid4);
endmodule

module DUT (input clk, 
            input rst,
            ... );

  wire dut_v1;
  wire dut_v2;
  wire dut_v3;
  wire dut_v4;

  A A_inst (.clk(clk), .rst(rst), .v1(dut_v1), .v2(dut_v2), .v3(dut_v3), .v4(dut_v4));
  B B_inst (.clk(clk), .rst(rst), .valid1(dut_v1), .valid2(dut_v2), .valid3(dut_v3), .valid4(dut_4));

endmodule

Here is what I implemented in my testbench. Firstly I created an interface definition and use uvmkit_register to bind it with DUT.


interface my_intf (
    input iclk, 
    input irst,
    output valid1,
    output valid2,
    output valid3,
    output valid4 );

    clocking master_cb @(posedge iclk);
           input irst;
           output valid1;
           output valid2;
           output valid3;
           output valid4;
    endclocking
endinterface

bind DUT my_intf my_intf_inst (.iclk(clk), 
                               .irst(rst),
                               .valid1(DUT.B_inst.valid1),
                               .valid2(DUT.B_inst.valid2),
                               .valid3(DUT.B_inst.valid3),
                               .valid4(DUT.B_inst.valid4)  );

`uvmkit_register_bind_intf_vif(my_intf, DUT, my_intf_inst)

and then I create standard driver and sqr also, to drive it in TestBench.

But the valid1/valid2/valid3/validr4 signal from waveform I drove is X because when I drive 1 on these signals at a certain clock, the original drive signal in the Design is 0. So my question is how to block this original drive behavior ?

2

In reply to zz8318:

You should get your DUT (top) into a state where it drives the signals like you want it to.

Or, you could just use force/release statements to force the value.

3

In reply to kernalmode1:

Could you please describe more detailed ? I am sorry I didn’t get what state do you mean ? Thank you !

4

In reply to zz8318:

A clocking block cannot be used to override the value on signal. Only the force statement can do that.

interface my_intf (
    input iclk, 
    input irst,
    inout valid1,
    inout valid2,
    inout  valid3,
    inout valid4 );
 
function void force_valid1(logic state);
    force valid1 = state;
endfunction
endinterface

Then you can call vif.force_valid1();

You might want to create one interface per signal making your code more reusable.
See my DVCon paper on this.