How to make sure clock generating correctly in usb3.0 Due to different clock for each layer?
Anyone have experince in USB3.0 Design Verification,please respond?
In reply to Subbi Reddy:
The specs should define the acceptable pulse widths and variations due to line losses.
You can use SVA to do such measurements. See
https://verificationacademy.com/forums/systemverilog/system-verilog-assertion-timing-checks-between-signals
Which issues are you having trouble with. You need to be more specific.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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