FATAL ERROR while loading design

SystemVerilog
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1

Hello All,

     I am facing the problem with the FATAL ERROR while loading design of SDRAM Memory controller. It is written as follow:

    # ** Fatal: (vsim-8451) sdr_xactor.sv(50): Virtual interface resolution cannot find a matching instance of interface 'sdr_top_if'.

    In the Verification using System Verilog, I am using Virtual interface into the interface file and during Declaration into the program Block , i am getting this Error.

    In the sdr_xactor.sv file and in 50th line, the statement is "@(negedge intf.sys_clk);" and since this line my execution has been stopped but my all files get compiled sucessfully.

    How to solve this Fatal Error,Please help me out ..

    Thanks in Advance.
2

You can think of a virtual interface kind of like a pointer that points to an actual interface instantiation somewhere in the design.
This error message is saying that no actual interface has been found that corresponds to this virtual interface. You have a pointer, that isn’t pointing to anything.

I would recommend starting by double checking your virtual interface declaration matches the actual interface you intend it to be pointing to. This includes if the actual interface is parametrized, the virtual interface must be parametrized with the same values.

3

Hello alexgran,

          Thank you for the Reply.

          I have declared the interface in the file in which i am working but its not instantiating my interface into the clocking block in my top interface file.

          what to do with it.

          Please help.
4

In reply to $@ndy:

You could help us help you by showing some relevant code.

The header of the interface declaration.
The interface instantiation.
The virtual interface declaration.