hi i am new to system verilog and test bench coding , i would like know the difference difference between drive and monitor in system verilog as i feel both of them doing same job ,name is different but at the bottom level both are just taking packets only ,please let me know the correct concept if i am wrong.
Have you read through the UVM Cookbook? Have you watched all of the UVM training courses? These are immensely valuable resources that can help you get started in the field of Verification.