Hi,
Recently I tried to design D Flip-Flop in SV along with interface and no exact SV TB environment in eda-playground platform. I am getting an error message and cannot figure it out.
/////////////////////////// Testbench Components \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
// File name : testbench.sv
`include "interface.sv"
module testcase(dff_if.TEST test_if);
initial
begin
test_if.sync_reset;
test_if.load_d(1);
test_if.load_d(0);
test_if.load_d(1);
#10 $finish;
end
endmodule
// File name : top.sv
module top;
bit clk;
always #10 clk = ~clk;
dff_if IF(clk);
testcase TB(IF);
dff RTL(IF);
initial
begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
// File name : interface.sv
interface dff_if(input bit clk);
logic rst;
logic d;
logic q;
parameter t_setup = 4, t_hold = 2;
clocking cb @(posedge clk);
default input #(t_setup) output #(t_hold);
output rst,d;
input q;
endclocking
modport DUV (input d,clk,rst, output q);
task sync_reset;
cb.rst <= 1;
cb.d <= $urandom;
repeat(2)
@(cb);
if(cb.q !== 0)
begin
$display("Reset isn't working");
$stop;
end
else $display("Reset is working fine");
endtask
task load_d;
input data;
cb.rst <= 0;
cb.d <= data;
repeat(2)
@(cb);
if(cb.q !== data)
begin
$display("Loading isn't working");
$stop;
end
else $display("Loading is working fine");
endtask
modport TEST(clocking cb,import task sync_reset(),import task load_d());
endinterface////////////////////////// Design Part \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
// File name : design.sv
module dff(dff_if.DUV duv_if);
always@(posedge duv_if.clk)
begin
if(duv_if.rst)
duv_if.q <= 0;
else duv_if.q <= duv_if.d;
end
endmodule///////////Error message\\\\\\\\\\\\\\
# Loading sv_std.std
# Loading work.dff(fast)
# Loading work.testcase(fast)
# ** Fatal: (vsim-3695) The interface port 'duv_if' must be passed an actual interface.
# Time: 0 ns Iteration: 0 Instance: /dff File: design.sv Line: 11
# FATAL ERROR while loading design
# Error loading design
#
# End time: 13:26:57 on Dec 23,2022, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
Exit code expected: 0, received: 1
