Creating an array of sequences

SystemVerilog
,
1

Hi,

I have uvm sequences with the names design_0_seq, design_1_seq, which are derived from uvm_reg_sequence.

I’m trying to create an array of sequences using the following piece of code:

uvm_reg_sequence sequence_array[NUM_SEQ];
string sequence_name [NUM_SEQ];

for (int i=0; i < NUM_SEQ; i++)
begin
sequence_name[i] = {“design_”,i,“_seq”};
sequence_array[i] = ($psprintf(“%s”),sequence_name[i])::type_id::create($sformatf(“sequence_array[%0d]”,i));
end

I’m observing syntax error on the line: sequence_array[i] = ($psprintf(“%s”),sequence_name[i])::type_id::create($sformatf(“sequence_array[%0d]”,i)); at the token ‘::’

The intended behavior is

sequence_array[0] = design_0_seq::type_id::create(“sequence_array[0]”);
sequence_array[1] = design_1_seq::type_id::create(“sequence_array[1]”);

Is there a way to fix this ?

Thanks,

2

In reply to hsaxena:

SystemVerilog does not allow you to form an identifier name from a string. But fortunately you are using the UVM; the `uvm_objects_util macro that registers the sequence with the factory gives you a way to construct a class (This article about the OVM provides some background). For unparameterized classes, that macro registers both a type and a string name to look up the class you want to construct.

uvm_factory f;
f = uvm_factory::get();
for (int i=0; i < NUM_SEQ; i++)
  begin
    sequence_name[i] = {"design_",i,"_seq"};
    if(!$cast(sequence_array[i], f.create_object_by_name(
        .requested_type_name(sequence_name[i]), .name($sformatf("sequence_array[%0d]",i)))
    `uvm_error("BADREQTYPE", $sforamtf("Requested type %s is not derived from uvm_reg_sequence", sequence_name[i])
  end

The $cast is needed because create_object_by_name always returns uvm_object.

3

In reply to dave_59:

Thank you Dave, this is exactly what I was looking for.