Creating an array of sequences

SystemVerilog
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2

In reply to hsaxena:

SystemVerilog does not allow you to form an identifier name from a string. But fortunately you are using the UVM; the `uvm_objects_util macro that registers the sequence with the factory gives you a way to construct a class (This article about the OVM provides some background). For unparameterized classes, that macro registers both a type and a string name to look up the class you want to construct.

uvm_factory f;
f = uvm_factory::get();
for (int i=0; i < NUM_SEQ; i++)
  begin
    sequence_name[i] = {"design_",i,"_seq"};
    if(!$cast(sequence_array[i], f.create_object_by_name(
        .requested_type_name(sequence_name[i]), .name($sformatf("sequence_array[%0d]",i)))
    `uvm_error("BADREQTYPE", $sforamtf("Requested type %s is not derived from uvm_reg_sequence", sequence_name[i])
  end

The $cast is needed because create_object_by_name always returns uvm_object.