Constraint inside question

SystemVerilog
1

How to implement that one element is inside some arrays ? I mean the element could be inside array0, or array1, or array2… as shown below


constraint
{
  m_ele inside {my_arr0} || m_ele inside {my_arr1} || m_ele inside {my_arr2};
}

How to do that ?

2

In reply to zz8318:

Doesn’t what you have work for you ? The below seems to work fine for me:



module test();
  int a ;
  int b[$] = {1,2,3,4,5};
  int c[$] = {6,7,8,9,10};
  
  initial begin
    
    std::randomize(a) with {
      { a inside {b} || a inside {c} };
    };
    $display("a is %0d",a);
  end
    
endmodule
3

In reply to KillSteal:

It’s better to use in the constraint. I will take a try

4

In reply to zz8318:
you should use the following constraint for m_ele can pick value from the either of the array.
You can also add the distribution, based on your requirements.


constraint
{
  m_ele inside {my_arr0 ,my_arr1,my_arr2};
}
5

In reply to kddholak:

Cool. I just use it. Thank you

6

In reply to zz8318:

The inside operator takes cares of the Logical OR ( || ) Operation internally .

Refer LRM :: 11.4.13 Set membership operator