Constraint inside question

SystemVerilog
2

In reply to zz8318:

Doesn’t what you have work for you ? The below seems to work fine for me:



module test();
  int a ;
  int b[$] = {1,2,3,4,5};
  int c[$] = {6,7,8,9,10};
  
  initial begin
    
    std::randomize(a) with {
      { a inside {b} || a inside {c} };
    };
    $display("a is %0d",a);
  end
    
endmodule