Concatenation

SystemVerilog
1

Hi all,

Here is my code in which I am trying to concatenate a and b into c but not able to do so. Please help.

My code:

class abc;
  rand bit [1:0] a;
  rand bit [1:0] b;
bit [3:0] c;
//bit c = {a,b};
  constraint A { a[1] == 1; a[0] == 0;}
  constraint B { b [1] ==1;}
  bit [3:0]  c = {a,b};
  /*function void display();
    $display("a = %b", a);
    $display("b = %b", b);
    endfunction*/
  
  function void displayA();
    $display("c = %b", c);
    endfunction
  
   
  
endclass

module tb;
 initial begin
   repeat (3) begin
   
abc xyz;
   xyz = new();
   xyz.randomize();
   //xyz.display();
     xyz.displayA();
   end 
   
   
 end
endmodule
2

In reply to ReshiRazdan90:

Please use code tags to make your code easier to read. I have added them for you.

You have two choices. You can declare c as rand and add a constraint:

class abc;
  rand bit [1:0] a;
  rand bit [1:0] b;
  rand bit [3:0] c;
  constraint C { c == {a,b}; }
  constraint A { a[1] == 1; a[0] == 0;}
  constraint B { b [1] ==1;}
endclass

Or you can use post_randomize();

class abc;
  rand bit [1:0] a;
  rand bit [1:0] b;
  bit [3:0] c;
  constraint A { a[1] == 1; a[0] == 0;}
  constraint B { b [1] ==1;}
  function void post_randomize();
    c = {a,b};
  endfunction
endclass
3

In reply to dave_59:

Thanks a lot Dave. Appreciated.

Yes, I did it with second method only.