Concatenation

SystemVerilog
2

In reply to ReshiRazdan90:

Please use code tags to make your code easier to read. I have added them for you.

You have two choices. You can declare c as rand and add a constraint:

class abc;
  rand bit [1:0] a;
  rand bit [1:0] b;
  rand bit [3:0] c;
  constraint C { c == {a,b}; }
  constraint A { a[1] == 1; a[0] == 0;}
  constraint B { b [1] ==1;}
endclass

Or you can use post_randomize();

class abc;
  rand bit [1:0] a;
  rand bit [1:0] b;
  bit [3:0] c;
  constraint A { a[1] == 1; a[0] == 0;}
  constraint B { b [1] ==1;}
  function void post_randomize();
    c = {a,b};
  endfunction
endclass