Can I have assertions in constant function

SystemVerilog
,
1

I was wondering if it’s legal to have assertion in constant function. I couldn’t find an issue in the LRM but when I compiled the code in one of the three major simulators it says its not supported. I am trying to determine if this is an LRM issue or tool issue. Thanks

Code:

package test_pkg;

function automatic int logb2
(
input int value
);

  if (value >= 1)
    begin
       value = value -1;
               
         for (logb2 = 0; value > 0; logb2++)
           value = value >> 1;
       
       return(logb2);
    end
  else
    begin
       assert (value >= 1) else $error("%m logb2 function issue with computation logb2 of %d\n", value); 
    end

endfunction // logb2

endpackage:test_pkg

2

In reply to noel:
We don’t discuss specific tools is this forum, but your code looks legal SV.
Immediate assertions can be in functions, tasks, and classes. Basically, anywhere an “if” statement is allowed.

1800’2017 “The immediate assertion statement is a test of an expression performed when the statement is executed in the procedural code. The expression is nontemporal and is interpreted the same way as an expression in the condition of a procedural if statement. In other words, if the expression evaluates to X, Z, or 0, then it is
interpreted as being false, and the assertion statement is said to fail. Otherwise, the expression is interpreted as being true, and the assertion statement is said to pass or, equivalently, to succeed."

Ben systemverilog.us

3

In reply to noel:

I was wondering if it’s legal to have assertion in constant function. I couldn’t find an issue in the LRM but when I compiled the code in vcs it says its not supported. I am trying to determine if this is an LRM issue or tool issue. Thanks
Code:


package test_pkg;
function automatic int logb2 
(
input int value
);
if (value >= 1)
begin
value = value -1;
for (logb2 = 0; value > 0; logb2++)
value = value >> 1;
return(logb2);
end
else
begin
assert (value >= 1) else $error("%m logb2 function issue with computation logb2 of %d\n", value); 
end
endfunction // logb2
endpackage:test_pkg

May be it is something specific to VCS alone ?? I see it working perfectly fine with Cadence simulator…

4

In reply to Subrahmanyam:

xcelium> run
xmsim: *E,ASRTST (./testbench.sv,16): (time 2 NS) Assertion test_pkg.logb2.__assert_1 has failed
test_pkg.logb2 logb2 function issue with computation logb2 of 0

5

In reply to Subrahmanyam:

We don’t discuss tools in this forum.
If you must refer to a tool, don’t use the tool’s name, just say something like “a simulation tool” says…

The moderator may delete that post. Tool issues must be discussed with the vendor.
Ben systemverilog.us

6

In reply to ben@SystemVerilog.us:

Thanks I corrected my original post and removed the name of the simulator. It works with 2 other major simulators. I will need to check synthesis and other tools.

7

In reply to noel:

1800’2017::20.8.1 Integer math functions
The system function $clog2 shall return the ceiling of the log base 2 of the argument (the log rounded up to an integer value). The argument can be an integer or an arbitrary sized vector value. The argument shall be treated as an unsigned value, and an argument value of 0 shall produce a result of 0. This system function can be used to compute the minimum address width necessary to address a memory of a given size or the minimum vector width necessary to represent a given number of states.
For example:
integer result;
result = $clog2(n);

I tried it Edit code - EDA Playground
and it seems that some simulators support the $clog2(n) function.
I believe that your error is in the recursive use of the function in your package.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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