Is it possible to format the function call using $sformatf() in system verilog.
Assuming I have predefined functions, func1, func2, func3 etc.
I want to call them while iterating a loop, can I format this call using sformatf?
something like:
initial begin
for(int i = 1; i< 4; i++)begin
$sformatf("func%0d",i);
end
end
are there any other ways to achieve function calls from the string names.
In reply to yourcheers:
SystemVerilog is not an interpretive language—you cannot create statements from strings.
If you could explain in more detail what you are trying to accomplish there might be other approaches. See the XY Problem.
In reply to dave_59:
I have design with many registers with incremental numbering, example reg1, reg2, reg3, etc. I have a ral model with the same naming.
I had generated this names from string processing and stored in an array. I want to use that processed strings to index the registers to program them.
example:
string array[$] = {reg0, reg1, reg2};
foreach(array[i])begin
ralmodel.< I want to use the string from the array[i] to index the ral model >.write();
end
In reply to yourcheers:
If you are using the UVM’s RAL, it has a way to lookup a register by a string name because the register model includes the name in its database.
uvm_reg reg, array[$];
for(int i = 1; i< 4; i++) begin
reg = regmodel.get_reg_by_name( $sformatf("reg%0d", num) );
if (reg !=null)
array.push_back(reg);
else
`uvm_error(...);
end
...
foreach(array[i])
array[i].write();