In reply to yourcheers:
SystemVerilog is not an interpretive language—you cannot create statements from strings.
If you could explain in more detail what you are trying to accomplish there might be other approaches. See the XY Problem.
In reply to yourcheers:
SystemVerilog is not an interpretive language—you cannot create statements from strings.
If you could explain in more detail what you are trying to accomplish there might be other approaches. See the XY Problem.