Can I format the function call using $sformatf in systemverilog

SystemVerilog
4

In reply to yourcheers:
If you are using the UVM’s RAL, it has a way to lookup a register by a string name because the register model includes the name in its database.

uvm_reg reg, array[$];
for(int i = 1; i< 4; i++) begin
  reg = regmodel.get_reg_by_name( $sformatf("reg%0d", num) );
  if (reg !=null)
     array.push_back(reg);
  else
     `uvm_error(...);
end
...
foreach(array[i]) 
   array[i].write();