Array randomization

SystemVerilog
,
1

I have array bit [15:0] data.
I want to randomize it in such a way that , next data should be…

1st data → 16’h01_00;
2nd data → 16’h03_02;
3rd data → 16’h05_04;
. .
. .
. .
How to write constraint for this?

2

In reply to Kishan_123:

This is not a random pattern; you do not need constraints for this.

class A;
  bit [15:0] data;
  bit [7:0] counter
  function void pre_randomize;
    data[7:0]  = counter++;
    data[15:8] = counter++;
  endfunction
endclass
3

In reply to dave_59:

Thanks Dave.

If array width is configurable like 8,16,32,64. then i have written like this.

bit [7:0] counter;
  function void pre_randomize;
    data.rand_mode(0);
    if(width==8) begin
    data[7:0]  = counter++;
    end  
    if(width==16) begin
    data[7:0]  = counter++;
    data[15:8] = counter++;
    end
    else if(width==32) begin
    data[7:0]  = counter++;
    data[15:8] = counter++;
    data[23:16] = counter++;
    data[31:24] = counter++;
    end 
    else if(width==64) begin
    data[7:0]  = counter++;
    data[15:8] = counter++;
    data[23:16] = counter++;
    data[31:24] = counter++;
    data[39:32] = counter++;
    data[47:40] = counter++;
    data[55:48] = counter++;
    data[63:56] = counter++;
    end  
   endfunction

but this is not good way to code. can you help me to do it in more generic way?

4

In reply to K_123:


class a;
  rand bit[7:0] data_q[$];
  int size =2; //user controlled, not rand, legal values 1,2,3,4 for 32 bit data size
  bit [31:0] data; //final output 
  constraint data_size_c {
    data_q.size() == size;
    foreach (data_q[i]) if (i!=0) {data_q[i] ==  data_q[i-1] +1;}
    data_q[0] == const'(data_q[$]) + 1;
  }
  
  function void post_randomize();
    //data = {<<8{data_q}};
    foreach(data_q[i]) data[i*8+:8] = data_q[i] ;
  endfunction:post_randomize
endclass:a

you can parameterize the data width, something like
bit[MAX:0] data ;
and use any value on size…no change to constraints

5

In reply to K_123:

That’s new information.

function void pre_randomize;
    for(int i = 0;i<width'i+=8)
    data[i+:8]  = counter++;
endfunction

BTW, Please use code tags making your code easier to read. I have added them for you.

6

In reply to dave_59:

Thanks Dave

7 
class abc;
  rand bit [15:0] data;
  
  constraint data_c {data[15:8]==data[7:0]+1;};
  constraint data_valid {data[7:0]==const'(data[7:0]) +2;};
endclass

module top;
  abc a1;
  
  initial begin
    a1=new();
    for (int i=0; i<10;i++) 
      begin
        
        assert(a1.randomize());
        $display("data=%h",a1.data);
      end
  end
endmodule

I use this code, but output is :

# vsim -voptargs=+acc=npr
# run -all
# data=0302
# data=0504
# data=0706
# data=0908
# data=0b0a
# data=0d0c
# data=0f0e
# data=1110
# data=1312
# data=1514
# exit

which modification is required to cover 01_00?

8

In reply to juhi_p:

You can either start with initializing
data[7:0] = -2;, or write a more complex constraint

  constraint data_valid {
       if const'(data[15:8]==0)
          data[7:0] == 0;
       else
          data[7:0]==const'(data[7:0]) +2;
}
9

In reply to dave_59:

initializing data[7:0]=-2 didn’t work. but other solution did work.Thanks.

10

You could just initialize 0th element to 'h101 and keep adding 'h202 to previous element.