Array randomization

SystemVerilog
,
3

In reply to dave_59:

Thanks Dave.

If array width is configurable like 8,16,32,64. then i have written like this.

bit [7:0] counter;
  function void pre_randomize;
    data.rand_mode(0);
    if(width==8) begin
    data[7:0]  = counter++;
    end  
    if(width==16) begin
    data[7:0]  = counter++;
    data[15:8] = counter++;
    end
    else if(width==32) begin
    data[7:0]  = counter++;
    data[15:8] = counter++;
    data[23:16] = counter++;
    data[31:24] = counter++;
    end 
    else if(width==64) begin
    data[7:0]  = counter++;
    data[15:8] = counter++;
    data[23:16] = counter++;
    data[31:24] = counter++;
    data[39:32] = counter++;
    data[47:40] = counter++;
    data[55:48] = counter++;
    data[63:56] = counter++;
    end  
   endfunction

but this is not good way to code. can you help me to do it in more generic way?