Problem with the above code: Since i am using edge as my comparing some cases property fails incorrectly, how can I use a assert property for time delay based on level sensitivity.
Problem Statement: When Signal A is de-asserted (from 0 to 1)
and within 700ns Signal B should be de-asserted (from 1 to 0).
This property should be re-usuable.
Problem with the above code: Since i am using edge as my comparing some cases property fails incorrectly, how can I use a assert property for time delay based on level sensitivity.
I don’t understand the issue. Elaborate with an example.
Ben systemverilog.us
Problem Statement: When Signal A is de-asserted (from 0 to 1)
and within 700ns Signal B should be de-asserted (from 1 to 0).
This property should be re-usuable.
I don’t understand the issue. Elaborate with an example.
Ben systemverilog.us
*** I am not able to attach an image here which can probably explain the corner case better**
Example Corner Case:
When the (posedge a) happens and if the value of b is already low(0), what it does is it looks for the next negedge of b and calculates the delay. This would cause an incorrect failure, since b is already low the property shouldn’t have failed
I have the solution if i use a clock but i am trying to find a way without using one
The following code doesn’t trigger the assertion for the actual failing case:
Below are links to the testbench and image. Seems tot work OK.
If you have trouble putting the image on a web site (like google photo), you may email your test code and image at ben@SystemVerilog.us